The present invention relates to a MOS circuit suited for lowering power dissipation. More particularly, it relates to a CMOS circuit which can lower power dissipation in the non-operating state, and also to an information processor using the same.
Heretofore, methods for reducing power dissipation in an information processor constructed of a large-scale integrated circuit, e.g., a microcomputer, have included a method wherein the supply of electric power to a circuit is stopped for a period during which that circuit need not operate, and a method wherein the clock frequency is lowered or the supply of clock pulses is stopped in the case of a circuit, such as a CMOS circuit, in which the power dissipation is proportional to the clock frequency. Regarding the first method for realizing the stopping of the power supply, a measure as shown in FIG. 1 is sometimes taken in which a path for electric power supply to the interior is disconnected through a switching circuit 3 that is controlled by a signal from a terminal 2. A block 4 in the figure is a circuit which is operating at all times, and a block 5 is a circuit to which the electric power supply is stopped when it need not operate. Electric power is dissipated when current has flowed from a power source terminal 1 to a ground terminal 1'. Therefore, when the operation of the block 5 is unnecessary, the switching element 3 is brought into the turn-off state by the control signal 2, thereby to cut off the path which extends from the terminal 1 to the terminal 1' through the block 5. Thus, the reduction of the power dissipation is achieved. In this case, there are involved such problems that all the contents of a storage device included in the block 5 are destroyed, that the supply of voltage to the block 5 lowers due to the resistance etc. possessed by the switching element 3, and that a period of time in the unit of milliseconds is taken until the electric power supply is stabilized at recovery, so the response becomes slow.
There will now be discussed the method which lowers the clock frequency or stops the supply of clock pulses in a CMOS circuit. In contrast to the foregoing method of stopping the electric power supply, this method is free from the problems of the lowering of the supply voltage and the slow response at recovery. Moreover, the stored contents are protected when all circuits constituting a system are static circuits.
The power dissipation of the CMOS circuit is broadly classified into a component attributed to a quiescent current which flows from the side of a p-type field effect transistor (pMOS) to the side of an n-type field effect transistor (nMOS) in such a manner that both the pMOS and the nMOS are in their "on" states temporarily when an input signal has changed, and a component attributed to a charge/discharge current into or from a capacitive load coupled to the output end of the circuit. Since the quiescent current is, in general, one or more orders smaller than the charge/discharge current, the latter may be regarded as determining the power dissipation of the CMOS circuit. Now, letting C.sub.i denote the output capacitance of the i-th in the circuit system, f.sub.i denote the frequency at which the output of the circuit changes, and V denote the supply voltage, the power dissipation P of this system becomes: ##EQU1## It is accordingly understood that the output change frequency f.sub.i may be lowered in order to reduce the power dissipation P. To the end of lowering the individual output change frequencies f.sub.i, the clock frequency of the circuit system may be lowered.
The MOS circuit is classified into a static circuit in which the voltage level of the input/output signal of a circuit comprised therein is definite even when no signal changes, and a dynamic circuit whose logic is activated by a clock pulse.
In general, when it is intended to achieve the same function as that of a logic circuit including dynamic MOS circuits, by the use of a logic circuit consisting entirely of static MOS circuits only, the number of elements becomes larger in the case of realizing the logic circuit with only the static circuits. In integrated circuits, the scale of integration has enlarged. Moreover, the scale of a circuit to be mounted thereon has enlarged still more. From the viewpoint of the number of elements, therefore, the dynamic circuits need to be used.
With the dynamic circuit employing CMOS transistors, however, when the clock frequency is lowered with the objective of reducing the power dissipation attendant upon charge/discharge, the problem occurs that the quiescent current increases to augment the power dissipation attendant thereupon. FIG. 2A shows a dynamic inverter circuit 10 which employs CMOS transistors. The circuit 10 is constructed of a series connection which consists of two pMOS's Q.sub.P1 and Q.sub.P2 and two nMOS's Q.sub.N1 and Q.sub.N2. An input signal I is applied to the gates of the transistors Q.sub.P1 and Q.sub.N2, while a clock .phi. and a clock .phi. obtained by inverting the former are respectively applied to the gates of the transistors Q.sub.N1 and Q.sub.P2. When the clock .phi. at "1" (high level) and .phi. is at "0" (low level), a signal OUT which is opposite in polarity to the input signal I is provided, and when .phi. becomes "0" and .phi. becomes "1", the status of the circuit before the changes of these clocks is retained. In this circuit, when the supply of the clocks is stopped and the status corresponding to .phi. of "0" and .phi. of "1" is held, the pMOS Q.sub.P2 and nMOS Q.sub.N1 which receive these clocks as gate signals fall into "off"states, and the output is in a floating state and holds an output voltage level with charges stored before. As long as the condition of stopping the clocks continues, the charges stored in an output capacitance C are gradually discharged as a leakage current. Therefore, the signal OUT shifts to a voltage level intermediate between "1" and "0" as illustrated in (c) of FIG. 2B. When, at this time, the output OUT of the dynamic circuit is connected to the input of a static inverter circuit 12, an input voltage to this inverter circuit 12 becomes the intermediate level, so that a pMOS Q.sub.P3 and an nMOS Q.sub.N3 fall into "on" states simultaneously, and a quiescent current flows through both the transistors for a long period of time T as illustrated in (d) of FIG. 2B. As a result, the quiescent current which is negligible with respect to the charge/discharge current during the normal operation cannot be ignored, and the power dissipation, as a whole, becomes greater than that attributed to the charge/discharge current during the operation. The prevention of the quiescent current during the cessation of the supply of the clocks is accordingly desirable in case of relieving the power dissipation by the control of the clock supply in the microcomputer which employs the CMOS transistor circuit.
At the very beginning, in the case where the control of the clock supply is applied to the microcomputer, it is desirable that the control of timings for starting and stopping the supply of the clocks can be simply performed.